Beyond CMOS: From Devices to Systems

• Date/Time
  Date(s) - 05/06/2017 - 06/06/2017
  All Day

  Location
  Kogan Auditorium, Meyer Building (EE)

  Categories No Categories

  
  

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  Research Workshop of the Israel Science Foundation (ISF)
  

  2017 Stephen and Sharon Seiden Frontiers in Engineering and Science Workshop:
  

  Beyond CMOS: From Devices to Systems
  

     

  Technion, Haifa, Israel on 5-6 June 2017

  Program

  Registration is now open! 

  Beyond CMOS: From Devices to Systems. Emerging solid state memories will extend CMOS technology. Including Device Physics, Circuits, Architecture, Reliability, Security, and Systems.
  These technologies include RRAM, PCM, 3D Xpoint, STT MRAM, CBRAM, Memristors, and others.

  This workshop will bring together researchers and executives from academia and industry to discuss the different implications of emerging solid state memories on computer industry.

  Conference Chairs:

  Eby G. Friedman, ECE University of Rochester

  Avinoam Kolodny, EE Technion

  Shahar Kvatinsky, EE Technion

  Confirmed speakers include:

  Alyssa Apsel Cornell, USA Alon Ascoli Technische Universität Dresden, Germany Leon Chua University of California, Berkeley, USA Ramez Danial Technion, Israel Massimiliano Di Ventra University of California, San Diego, USA Eby Friedman University of Rochester, USA Joseph S. Friedman University of Texas at Dallas, USA Pierre-Emmanuel Gaillardon University of Utah, Salt Lake City, USA Giacomo Indiveri University of Zurich | ETH Zurich, Switzerland Engin Ipek University of Rochester, USA Edwin Chihchuan Kan Cornell, USA Michael Kozicki Arizona State University, USA Hai Li Duke University, USA Michal Lipson Columbia University, USA Giovanni De Micheli EPFL, Switzerland Thomas Mikolajick TU Dresden | Namlab, Germany Onur Mutlu Carnegie Mellon University | ETH Zurich, Switzerland Stuart Parkin Max Planck Institute, Germany Damien Queriloz Paris-Sud University, France Jennifer Rupp MIT, USA Sabina Spiga National Research Council, Italy Mircea R. Stan University of Virginia, USA Ronald Tetzlaff Technische Universität Dresden, Germany Ioannis Vourkas Pontifical Catholic University of Chile, Chile Uri Weiser Technion, Israel Yuan Xie University of California at Santa Barbara, USA Eli  Yablonovitch University of California, Berkeley, USA Jianhua Joshua Yang University of Massachusetts, USA

  Amit Berman, Samsung Boaz Eitan, Q-Core Medical Avi Klein, Western Digital Suhas Kumar, HPE Pankaj Mehra, Western Digital Pei-Lin Pai, Winbond Technologies Amir Regev, Weebit-Nano Yakov Roizin, Tower Jazz Abu Sebastian, IBM

   

  About the Conference 

  Program

  Advancements in computer capabilities in the last fifty years had been closely linked to miniaturization of CMOS technology, while the underlying structure of digital computing systems has been based on von Neumann architecture, where the memory and execution units are logically and physically separated, using various types of interconnect for communication between them. Recently, device scaling has slowed down, while electrical interconnect has become both a performance bottleneck and a major source of power dissipation, which is currently the most critical limiter for technology growth. Conventional memory technologies, such as Flash, DRAM, and SRAM, are unable to keep up with market requirements for higher density and lower power. Flash memory has already achieved its physical limits, and cannot be scaled further, primarily due to its limited endurance.

  These problems can be addressed by emerging new semiconductor devices, such as Resistive Random Access Memory (RRAM), Conductive Bridge Random Access Memory (CBRAM), Phase Change Memory (PCM), Spin-Transfer Torque Magentoresistance Random Access Memory (STT-MRAM), memristors, 3D Xpoint and others. Since these technologies are useful both as memory cells and as novel switching circuits, they can be used to augment traditional CMOS gates and enable new computing systems.

  This workshop will bring together researchers and executives from academia and industry to discuss the different aspects of emerging solid state memories including device physics, circuits, architecture, reliability, security, software, and system. We believe that these technologies open opportunities for radical changes in all of the aforementioned aspects and that bringing together people from different disciplines can give better perspective on the influence of these technologies and be mutually inspiring.

  We will have speakers from all of these fields, including world-leading researchers and executives from industry who will discuss the commercialization aspects of these technologies. The speaker list covers speakers from all of the disciplnes and together they will cover all of the relevant issues that need to be considered when adding new technologies to existing systems and how these technlogies may enable new systems.

  We expect a large national and international audience to attend the workshop, including students who will present posters. The workshop is part of the "Stephen and Sharon Seiden Frontiers in Engineering and Science Workshop" annual event at the Technion and will be followed by the annual training school of EU COST Action IC-1401 MemoCIS. 

  
  

  Program
  

   
  

  Important dates:
  

  Poster submission (Extended!) 15^th April 2017
  *(Please submit a title, a list of authors including affiliations and an abstract – up to 1 page, here)
  Early bird registration                 15^th April 2017
  Poster acceptance notification    1^st May 2017
  Registration                               1^st May 2017

  location information:
  

  for help and more information please visit the folowing pages: 

  • Visiting Israel: here

  • Getting around: here 

  • Accomodation: here

  • Other recommendations: here

  For any questions or further assistance don't hesitate to contact Shahar, local chair ​or Liraz, local administration.

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